A prior art non-volatile memory cell 110 is shown in FIG. 1. The memory cell 110 comprises a semiconductor substrate 112 of a first conductivity type, such as P type. The substrate 112 has a surface on which there is formed a first region 114 (also known as the source line SL) of a second conductivity type, such as N type. A second region 116 (also known as the drain line) also of N type is formed on the surface of the substrate 112. Between the first region 114 and the second region 116 is a channel region 118. A bit line BL 120 is connected to the second region 116. A word line WL 122 is positioned above a first portion of the channel region 118 and is insulated therefrom. The word line 122 has little or no overlap with the second region 116. A floating gate FG 124 is over another portion of the channel region 118. The floating gate 124 is insulated therefrom, and is adjacent to the word line 122. The floating gate 124 is also adjacent to the first region 114. The floating gate 124 may overlap the first region 114 to provide coupling from the region 114 into the floating gate 124. A coupling gate CG (also known as control gate) 126 is over the floating gate 124 and is insulated therefrom. An erase gate EG 128 is over the first region 114 and is adjacent to the floating gate 124 and the coupling gate 126 and is insulated therefrom. The top corner of the floating gate 124 may point toward the inside corner of the T-shaped erase gate 128 to enhance erase efficiency. The erase gate 128 is also insulated from the first region 114. The cell 110 is more particularly described in U.S. Pat. No. 7,868,175 whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program of prior art non-volatile memory cell 110 is as follows. The cell 110 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 128 with other terminals equal to zero volt. Electrons tunnel from the floating gate 124 into the erase gate 128 causing the floating gate 124 to be positively charged, turning on the cell 110 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 110 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 126, a high voltage on the source line 114, a medium voltage on the erase gate 128, and a programming current on the bit line 120. A portion of electrons flowing across the gap between the word line 122 and the floating gate 124 acquire enough energy to inject into the floating gate 124 causing the floating gate 124 to be negatively charged, turning off the cell 110 in read condition. The resulting cell programmed state is known as ‘0’ state.
Exemplary voltages that can be used for the read, program, and erase operations in memory cell 110 is shown below in Table 1:
TABLE 1CG-unselOper-sameCG-EG-ationWLWL-unselBLBL-unselCGsectorunselEGunselSLSL-unselRead1.0-2 V    0 V0.6-2 V    0V/FLT0-2.6 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V0 V0V/FLTErase0 V0 V0 V0V    0 V0-2.6 V0-2.6 V11.5-12 V 0-2.6 V0 V0VPro-1 V0 V 1 uAVinh10-11 V  0-5 V0-2.6 V4.5-8 V0-2.6 V4.5-5 V    0-1V/FLTgramNote:“FLT” means floating
For programming operation, the EG voltage can be applied much higher, e.g. 8V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 6V, to reduce unwanted erase effect of the adjacent memory cells sharing the same EG gate of the selected memory cells.
Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell 310 is shown below in Table 2:
TABLE 2CG-unselOper-sameCG-EG-ationWLWL-unselBLBL-unselCGsectorunselEGunselSLSL-unselRead1.0-2 V    −0.5 V/0.6-2 V    0V/FLT0-2.6 V0-2.6 V0-2.6 V0-2.6 V0-2.6 V0 V0V/FLT0 VErase0 V0 V0 V0V    0 V0 V-2.6 V 0-2.6 V11.5-12 V 0-2.6 V0 V0VPro-1 V−0.5 V/ 1 uAVinh10-11 V 0-2.6 V0-2.6 V4.5-5 V0-2.6 V4.5-5 V    0-1V/FLTgram0 V
Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell 310 is shown below in Table 3:
TABLE 3CG-unselOper-sameCG-EG-ationWLWL-unselBLBL-unselCGsectorunselEGunselSLSL-unselRead1.0-2 V    −0.5 V/0 V0.6-2 V    0V/FLT0-2.6 V0-2.6 V0-2.6 V0-2.6 V 0-2.6 V0 V0V/FLTErase0 V−0.5 V/0 V0 V0V−(5-9) V 0-2.6 V0-2.6 V9-8 V0-2.6 V0 V0VPro-1 V−0.5 V/0 V 1 uAVinh 8-9 V 0-5 V0-2.6 V8-9 V0-2.6 V4.5-5 V    0-1V-FLTgram
For programming operation, the EG voltage is applied much higher, e.g. 8-9V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 5V, to reduce unwanted erase effects of the adjacent memory cells sharing the same EG gate of the selected memory cells.
Also known in the prior art are fully depleted silicon-on-insulator (“FDSOI”) transistor designs as shown in FIGS. 2-4. The FDSOI advantages includes a back gate (with buried oxide as a gate oxide) to modulate the threshold voltage (forward body bias or reverse body bias), an ultrathin un-doped channel that gives higher mobility and no random doping fluctuation. It has a ground plane on the back gate to adjust implant to adjust the threshold voltage. It also has a channel that is fully depleted to give better electrostatic control, lower drain-induced-barrier-lowering DIBL and short channel effect. It has minimum source and drain junction. Metal gate and channel length are also used to adjust threshold voltage.
FIG. 2 depicts FDSOI CMOS circuit cross section 210. FDSOI CMOS circuit 210 comprises silicon substrate 211, silicon insulators 216, FDSOI NMOS transistor 230, and FDSOI PMOS transistor 240.
FDSOI NMOS transistor 230 comprises gate 218, and source and drain 217. FDSOI NMOS transistor 230 further comprises p-well 212, buried oxide layer 213 (which is an insulator), and channel 215. Channel 215 is an undoped, fully depleted channel. During operation, buried oxide layer 213 minimizes any leakage out of channel 214. FDSOI NMOS transistor 230 further comprises p-well back gate terminal 219, which can be used to add a bias to p-well 212 such as to adjust the threshold voltage Vt of the NMOS 230.
FDSOI PMOS transistor 240 comprises gate 228, and source and drain 227. FDSOI PMOS transistor 240 further comprises n-well 222, buried oxide layer 223 (which is an insulator), and channel 225. Channel 225 is an undoped, fully depleted channel. During operation, buried oxide layer 223 minimizes any leakage out of channel 225. FDSOI PMOS transistor 240 further comprises n-well back gate terminal 229, which can be used to add a bias to n-well 222 such as to adjust the threshold voltage Vt of the PMOS 240.
FIG. 3 depicts FDSOI CMOS circuit cross section 310. FDSOI CMOS 310 circuit comprises silicon substrate 311, silicon insulators 316, FDSOI NMOS transistor 330, and FDSOI PMOS transistor 340.
FDSOI NMOS transistor 330 comprises gate 318, and source and drain 317. FDSOI NMOS transistor 330 further comprises n-well 312, buried oxide layer 313 (which is an insulator), and channel 315. Channel 315 is an undoped, fully depleted channel. During operation, buried oxide layer 313 minimizes any leakage out of channel 315. FDSOI NMOS transistor 330 further comprises n-well back gate terminal 319, which can be used to add a bias to n-well 312 such as to adjust the threshold voltage Vt of the NMOS 330.
FDSOI PMOS transistor 340 comprises gate 328, and source and drain 327. FDSOI PMOS transistor 340 further comprises p-well 312, buried oxide layer 323 (which is an insulator), and channel 325. Channel 325 is an undoped, fully depleted channel. During operation, buried oxide layer 323 minimizes any leakage out of channel 325. FDSOI PMOS transistor 340 further comprises p-well back gate terminal 329, which can be used to add a bias to p-well 322 such as to adjust the threshold voltage Vt of the PMOS 340.
FIG. 4 depicts FDSOI and bulk CMOS hybrid MOS circuit cross section 410. Bulk CMOS refers to standard PMOS and NMOS transistor on bulk silicon. Hybrid MOS circuit 410 comprises silicon substrate 411, silicon insulators 416, FDSOI NMOS transistor 430 and NMOS transistor 440. NMOS transistor 440 is a traditional NMOS transistor and not an FDSOI NMOS transistor.
FDSOI NMOS transistor 430 comprises gate 418, and source and drain 417. FDSOI NMOS transistor 430 further comprises p-well 412, buried oxide layer 413 (which is an insulator), and channel 415. Channel 415 is an undoped, fully depleted channel. During operation, buried oxide layer 413 minimizes any leakage out of channel 415. FDSOI NMOS transistor 430 further comprises p-well back gate terminal 419, which can be used to add a bias to p-well 412 such as to adjust the threshold voltage Vt of the NMOS 430.
NMOS transistor 440 comprises gate 428, and source and drain 427. NMOS transistor 440 further comprises p-well bulk 422 and doped channel 423. NMOS transistor 440 further comprises p-well bulk terminal 429, which can be used to add a bias to p-well bulk 422.
To date, fully depleted silicon-on-insulator transistor designs have not been used in flash memory systems. What is needed is a flash memory system that utilizes fully depleted silicon-on-insulator transistor designs. What is further needed is a partitioned flash memory chip that comprises a bulk region and an FDSOI region to maximize area and minimize leakage.